Master's student in Electrical Engineering and Information Technology at ETH Zürich. Interested in embedded systems and digital hardware design.
Extended a RISC-V CVE2 core with a boot-time selectable reliable RV32E mode and fault detection through repeated instruction execution, reducing fault-injection failure rate from 24% to 1% and closing timing at 113.8 MHz post-layout in IHP SG13G2.
Built a configurable ISA-level fault-injection framework in Spike, automating large-scale campaigns with golden-run comparison and differential trace generation to identify fault propagation and program-output mismatches.
Designed a hardware accelerator for the PHOTON-Beetle AEAD scheme, integrated as an AXI peripheral on an Ibex-based SoC and verified against NIST Known Answer Test vectors, achieving a 42x speedup over software execution.